Microlithographic patterning of integrated circuits has made great improvements in recent years. Prototype devices with dimensions less than 100 nm in width have been demonstrated, and are expected to enter routine production soon.
These integrated devices are typically assembled sequentially, through a series of process steps that carry out the necessary deposition, patterning, and etching steps that result in the final device. A contemporary microdevice often comprises more than 25 distinct layers, each with its own mask to define feature dimensions, and a sequence of process steps that the entire wafer must undergo to create the desired layer.
Extremely high resolution lithography can be carried out using electron beam (or E-beam) lithography. This prior art technique for fabricating microdevices is illustrated in FIG. 1. In this example, a partially fabricated substrate 100, comprising an underlying substrate 110 with the previously fabricated layers 120 containing microstructures 112 and 122, is coated with a uniform layer 130 of the material to be processed (e.g. metal, polysilicon, etc.), and then coated with a polymer layer 150, commonly called a resist, sensitive to electron beam exposure. The sensitive layer 150 is then exposed to patterns of electron beams 160, as shown in FIG. 1a, where the geometric arrangement and dose defines the pattern to be formed. The exposed material is then chemically processed, or developed, and, as shown in FIG. 1b, the unexposed regions 152 are left on the substrate. These serve as protection for portions of the material to be patterned 130, so that after subsequent processing, as shown in FIG. 1c, only the protected portions 132 of the material 130 to be processed remain.
Although E-beam lithography can produce extremely high resolution patterns, the typical throughput of an E-beam machine is very slow. Beams must be directed to each spot on the wafer in sequence, which makes the process generally slow and impractical for large numbers of microstructures. Instead, in optical lithography, the E-beams 160 are replaced by an optical image of a mask, which exposes the sensitive film 150 in parallel. However, optical imaging techniques do not have the same resolution as E-beam systems, and fabricating nanostructures (features with dimensions on the order of 100 nm or smaller) in these layers has been growing exponentially more expensive. As a result, alternative paradigms for lithography of these layers have been investigated.
One example of these novel technological patterning paradigms is nanoimprint technology. In nanoimprint techniques, a master pattern is formed by a high resolution patterning technique, such as E-beam lithography. These high resolution masters are then used to create a corresponding pattern on the IC layer without the use of an imaging step, but with some kind of stamping or printing technique. This is in principle very similar to techniques used for creating the microscopic patterns found on compact discs (CDs).
The most straightforward illustration of this was developed by Stephen Chou et al, and is illustrated in FIG. 2. Chou's process would take the same layer to be processed 130, coated on a partially fabricated substrate 100, but coat the assembled substrate with a layer of a deformable polymer 250, as shown in FIG. 2a. The master template 210, with patterns of indentations 212 corresponding to locations where the final structures are desired, is fabricated by high resolution lithography techniques. The template 210 is then aligned over the partially fabricated substrate 100 and as shown in FIG. 2b, the two are pressed together. The deformable polymer 250 fills the indentations 212 in the master 210. The master is then removed, leaving a pattern of structures 252 on the partially fabricated substrate 100 as shown in FIG. 2c. Subsequent processing, such as etching, leaves the desired result of patterns 132 formed from layer 130, defined by the locations of the remaining material 252, as shown in FIG. 2d. Chou has demonstrated the reproduction of features as small as 10 nm using this technique.
C. Grant Willson et al. have proposed a variation on this technique as illustrated in FIG. 3. In this approach, the master 310 is transparent to ultraviolet light. This master 310 also contains indentations 312 patterned in the surface through a high resolution fabrication technique. As shown in FIG. 3a, Willson's process takes the same layer to be processed 130, coated on a partially fabricated substrate 100, but coats the assembled substrate with a layer of a deformable polymer 350 which is also sensitive to UV exposure. The transparent master 310 is pressed against the polymer 350 on layer 130 and partially fabricated substrate 100. This layer 350 deforms, filling the indentations 312 in the master 310 with material 352, while possibly leaving a thin layer 351 still between the surface of the master and the substrate. The polymer materials 351 and 352 are then cured and hardened using UV exposure 360, as shown in FIG. 3b. Then, as shown in FIG. 3c, the master is removed, leaving thicker material 352 over the portions of layer 130. Subsequent processing, such as etching, leaves the desired result of patterns 132 formed from layer 130, defined by the locations of the remaining material 352, as shown in FIG. 3d. 
A drawback to these techniques is that the master must be repeatedly used again and again in the formation of the desired material. This can lead to damage to the master through normal wear and exposure to contaminants. A common technique used to replicate diffractive structures used for gratings and other photonic devices involves the creation of replicas of a master grating. These methods involve the creation of a master from which replications are made by applying a thin vacuum deposited separation layer on the master. A metal coating is then deposited on top of the separation layer, and an epoxy coated substrate is placed on top of the layer-covered master. The combination is then cured and the process is completed when the replicated grating is separated from the master grating. This approach suffers from throughput limitations requiring vacuum depositions on the master. With this approach, the master suffers degradation only from the creation of multiple replicas; the replicas themselves are used in the actual fabrication process and are discarded when damaged.
George Whitesides et al. have developed a similar process using a replica, or template, made from poly(dimethylsiloxane) (PDMS) for applications that he calls “soft lithography”. They have also developed a variation of this process using an inking technique, to minimize damage to the template. This is similar in concept to the inking of rubber stamps commonly used in other conventional printing applications.
An example of this process is illustrated in FIG. 4. The master 400 with indentations 402 itself is not used directly, but is replicated as a polymer template 410 with raised sections 412 corresponding to the indentations 402. This polymer template 410 can be used directly for imprint lithography, and discarded if damaged through reuse. To achieve the same patterns 132 from a layer to be processed 130, coated on a partially fabricated substrate 100, Whitesides' process coats the assembled substrate with a layer of a special material 450 which is selected for certain chemical characteristics. As shown in FIGS. 4a and 4b, the template 410 is formed from PDMS by coating the master 400 with the material, either through spin coating or by some other coating and curing technique. Then, as shown in FIG. 4c, the template 410 is then bonded to a carrier 430 using some bonding layer 420, and removed from the master 400.
This template 410 is then “inked” with a thin layer of special chemicals 414 such that only the raised portions 412 of the template 410 are coated with the chemical 414, as shown in FIG. 4d. The template is then aligned and placed in close contact with the partially fabricated substrate 100 with partially fabricated microdevices also coated with a layer to be processed 130 and chemical layer 450, transferring the “ink” 414 to the substrate as shown in FIG. 4e. The material for the ink 414 and the layer 450 will be chosen to react, and leave an altered layer of material 452 in locations touched by the ink 414, as illustrated in FIG. 4f. This altered material 452 serves as a barrier to the reactions, protecting the layer 130 below. Subsequent processing leaves the desired result of patterns 132 formed from layer 130, defined by the locations of the altered material 452, as shown in FIG. 4g. 
Some of the problems with PDMS as a template that limit its applicability include limited resolution (about 200 nm) because of the difference in thermal expansion coefficient between the PDMS and the mold material, and limited throughput because of the time needed for curing. It also suffers from material incompatibility since it will stick to large areas of clean silicon.
In all of these fabrication techniques, the imprinting technique serves as a method for patterning a layer or film directly on the final substrate, e.g. a silicon wafer. The imprint master or template is used again and again to stamp out duplicate copies of nanostructures at low cost.
There can be undesirable consequences from using these techniques. For example, the definition of a particular layer with extremely fine structures with E-beam exposure will inherently risk irradiating the underlying layers to the electron beam as well. Care must be taken to insure that the electrical structures already created in the underlying layers are not damaged. The mechanical stamping of the master or the template onto the substrate must also be precisely controlled, or the fragile structures underneath can be strained or cracked. Keeping the master or replica free of defects as it is used again and again can also present problems.
Furthermore, processing the wafer itself layer by layer, although the standard fabrication technique for integrated circuits, may be less than optimal. For example, a metal or polysilicon layer may be best processed at a high temperature for the best results, but this degree of heating may damage or even melt the layers previously prepared on the substrate. Because all subsequent steps in the manufacture of the microdevice are deposited on the same substrate, however, these problems in process compatibility and their required compromises remain.
Some manufacturing processes in other industries avoid these problems by having separate manufacturing processes for different components, and then assembling these at a later stage of integration. The packaging of ICs is one example of such a dual process, in which the IC itself is prepared on a silicon wafer, and then cut from the wafer, and placed and bonded into a pre-prepared package. The preparation of the package and the IC follow two separate manufacturing processes until the bonding step is required.
Another example of this kind of dual processing or patterning is found in the common sticker. A pattern in ink is prepared on paper, plastic or some other substrate, and an adhesive applied that allows bonding to another substrate. Examples of this are very common, for example, as decorations in a scrapbook, as a label on a filing cabinet, or as a statement on an automobile bumper. Clearly, forcing a large object such as an automobile bumper to fit through a printing and patterning process to attach a simple humorous message would be awkward and very expensive. The bumper sticker is far more flexible and far less expensive.
Likewise, the separation of substrate preparation and even the fabrication of microstructures can be commonly seen. Embossed holograms, such as those found on common credit cards, have structures with sizes on the same order of magnitude as the wavelength of visible light (400-700 nm). These are easily created using a printing or mechanical stamping process, and can also be prepared with adhesives. They are then and attached to many other substrates, such as credit cards, bumper stickers, magazine pages, etc. that could not be used directly in a holographic fabrication process themselves. Integrated circuits themselves are also finding application when attached directly on the surface of various “smart cards”.
In a previous invention, described in U.S. patent application entitled “Molecular Transfer Lithography” and assigned Ser. No. 09/898,521, we have disclosed an invention separating the preparation and imaging in lithographic materials, and the subsequent steps of processing the image and transferring the pattern into the final substrate. This was done by the formation of the required latent image in photoresist on an intermediate carrier. The photoresist containing the latent image is then mechanically aligned and transferred to the location on the final substrate where the subsequent processing is to occur.
This separation of processing steps allows an inventory of pre-processed latent images to be formed that can be used upon demand without delay. These latent images are typically formed on flat carriers under optimized imaging conditions. It also allows the preparation to be carried out on the carrier using an optimized process without concern for the immediate consequences on the substrate, since the substrate is not part of the process. The only concern would be the interaction of residues and the substrate once they are brought together.
Although the prior techniques reflect a great degree of innovation and creativity, and can offer significant cost advantages over conventional lithographic processing techniques, there is a need for a technique that has many or all of the advantages of a nanoimprint technique but does not have the problems associated with reusing a master or template. Furthermore, although the previously disclosed molecular transfer lithography technique addresses some of these issues, the latent image formed was generally flat and did not have topographic structures corresponding to the topography desired on the final wafers.